1. Field of the Invention
The present invention relates to a semiconductor test apparatus for testing high-speed digital LSIs and, more particularly, to a current load circuit in a pin electronics circuit which is provided for each of the pin terminals of a high-speed digital LSI and applies a test signal for measuring an output signal issued from the LSI in response to the test signal.
2. Description of the Related Art
FIG. 4 is a circuit diagram showing the connection relationship between a pin electronics circuit and a device to be tested in a prior art semiconductor test apparatus. While FIG. 4 illustrates the pin electronics circuit for one pin terminal of the tested device, the a similar circuit is provided for each of pin terminals of the tested device. These pin electronics circuits are controlled under supervision of a controller comprising a CPU or the like so that, for example, when one pin electronics circuit supplies a test signal to the pin terminal connected thereto, the pin electronics circuit connected to another pin terminal measures an output signal issued from the associated pin terminal pin in response to the test signal. The configuration of such a semiconductor test apparatus is disclosed in, e.g., Japanese Patent Laid-Open No. 4-250373 and will not described here in detail.
In FIG. 4, denoted by 1 is a device to be tested, i.e., a high-speed digital LSI, 2 is an output buffer circuit provided in the tested device 1 and having an output impedance R, 3 is a pin electronics circuit of the semiconductor test apparatus, 4 is a driver circuit for outputting a test logical waveform to the tested device 1, 5 is a comparator circuit including two comparators for L and H levels, respectively, to compare an output waveform from the tested device 1 with an expected value and determine whether both the values coincide with each other, 6 is a current load circuit for applying a current load to the tested device 1 and used, e.g., when holding a pin terminal 1a connected to the pin electronics circuit 3 in a high-impedance state "Hz", 7 is a coaxial cable as a transmission line connecting the tested device 1 and the pin electronics circuit 3 and having a characteristic impedance 8 is a current load switching voltage generator, and S is a strobe signal for switching over the circuits 4 to 6 so that the circuits are selectively brought into an operative state depending on the test to be performed.
FIG. 5 is an enlarged view of the current load circuit 6 in the pin electronics circuit 3 shown in FIG. 4. Referring to FIG. 5, denoted by 9 is a source current load circuit for setting a value of the current (hereinafter referred to as source current Isource) introduced to the tested device 1, 10 is a sink current load circuit for setting a value of the current (hereinafter referred to as sink current Isink) drawn out of the tested device 1, and 11 is a diode bridge control circuit for selecting either one of the source current and the sink current in accordance with a voltage value V.sub.T from the current load switching voltage generator 8.
Assuming that the output voltage of the output buffer circuit 2 in the tested device 1 is V.sub.OUT, the sink current flows when there holds a relationship of; EQU V.sub.OUT &gt;V.sub.T -V.sub.D
and the source current flows when there holds a relationship of; EQU V.sub.OUT &gt;V.sub.T +V.sub.D
where V.sub.D is the potential across the diode of the diode bridge control circuit 71.
Signal waveforms produced in the circuit of FIG. 4 are shown in FIG. 6. Specifically, FIG. 6 illustrates typical input/output waveforms produced when the output impedance R of the output buffer circuit 2 is smaller than the characteristic impedance Z.sub.0 of the coaxial cable 7, in which; (a) in FIG. 6 illustrates the output waveform from the tested device 1 (i.e., the waveform observed at a point A in FIG. 4), and (b) in FIG. 6 illustrates the input waveform at an entry to the comparator circuit 5 when the output of (a) is received by the pin electronics circuit 3 (i.e., the waveform observed at a point B in FIG. 4).
As seen from (b) in FIG. 6, the input waveform (i.e., the waveform observed at the point B) becomes the so-called ringing waveform including an overshoot indicated by a voltage .DELTA.V.sub.1 and an undershoot indicated by a voltage .DELTA.V.sub.2 with a reflection.
It is here assumed that the rise time of the output waveform of the output buffer circuit 2 in the tested device is Tr and the distance from the point A to the point B in FIG. 4 is L. Also, the H-level output potential of the output buffer circuit 2 is V.sub.OH and the L-level output potential thereof is V.sub.OL (see (a) in FIG. 6).
The operation of the prior art semiconductor test apparatus will be described below. As the operating speed of the tested device 1 is increased, the rise time Tr of the output waveform of the output buffer circuit 2 is generally shortened. If there holds a relationship of: EQU L&gt;&gt;Tr/2.multidot..tau.
.tau.: signal transmission time per unit length of transmission line PA1 Z.sub.0 &gt;R
between the rise time Tr and the distance L from the output terminal (point A) of the tested device 1 to the input terminal (point B) of the comparator circuit 5, the transmission line is a distributed constant line. Under this condition, the output impedance R of the output buffer circuit 2 and the characteristic impedance Z.sub.0 of the coaxial cable 7 are related to each other by;
resulting in a mismatch therebetween. Thus, the input signal applied to the pin electronics circuit 3 is subject to reflections on the input transmission line, and the ringing waveform as shown in (b) of FIG. 6 results. This means that the test cannot be correctly performed.
In the prior art pin electronics circuit 3, the ringing waveform can be shaped by using the current load circuit 6. However, since the current load switching voltage generator 8 can be set to only one voltage value V.sub.T, it is only possible to shape either the overshoot indicated by .DELTA.V.sub.1 or the undershoot indicated by .DELTA.V.sub.2. An output waveform indicated by B.sub.1 in FIG. 7 represents the one that results when the voltage value V.sub.T of the current load switching voltage generator 8 is set such that the low level of the output waveform is clamped to a potential adapted to clip the undershoot. In FIG. 7, the ringing waveform including the undershoot indicated by a dot line is shaped.
Here, the voltage value V.sub.T of the current load switching voltage generator 8 is set to V.sub.T =V.sub.OL -V.sub.D in consideration of the voltage V.sub.D across the diode.
In short, the prior art semiconductor test apparatus constructed as described above has the problem that, although the current load circuit is used to shape the ringing waveform, it can be set to only one voltage value, which results in the ringing waveform including either an overshoot or an undershoot and hence a test cannot be correctly performed.